The present invention relates to a semiconductor device, and more specifically, to a technology of connecting gates to an N+ or P+ junction by the first connected wiring layer to prevent plasma damages during a plasma process.
In the manufacturing of general silicon semiconductors, a process for depositing or etching a thin film with plasma gas results in plasma damages which affect characteristics of unit elements on a wafer.
FIGS. 1a and 1b are diagrams illustrating plasma damages in a conventional semiconductor device.
A process for depositing a thin film which has been widely used in the semiconductor manufacturing process includes precipitating reactors on a wafer with an ionized plasma gas to form a new film. Also, a dry etching process for forming a desired pattern includes etching a specific material on a wafer with a plasma gas.
The plasma ion gas used in the above processes charges up conductive layer patterns on the wafer into positive ions. Since the plasma gas has positive (+) property, positive charges are continuously accumulated in a conductive layer covered with an insulating film during the process to attract negative particles.
A gate pattern 1 affects the characteristics of an insulating film less since the gate pattern 1 is covered with a thick insulating layer around a gate oxide 2. However, the gate oxide 2 having a thin thickness is formed close to a substrate which is a conductive layer.
When the gate pattern 1 is positively charged up, negative particles which are mostly electrons are attracted. These negative particles are trapped in the gate oxide 2 or flown into the gate pattern 1 through the gate oxide 2. Also, a discharge phenomenon occurs through the gate oxide 2 toward the substrate from the charged-up gate pattern 1.
The discharge phenomenon damages the gate oxide 2 to cause change in the characteristics of the semiconductor device, which is called plasma damages. As a result, the plasma damages generated during the manufacturing of semiconductor devices may change the device and design characteristics.
FIG. 2 is a graph illustrating threshold voltage increase of a NMOS transistor resulting from plasma damages in a conventional semiconductor device.
Referring to FIG. 2, (B) represents data measured after a first wiring layer is formed, and (C) represents data measured after a second wiring layer is formed. (D) represents data measured after a first passivation material is deposited and patterned, and (E) represents data measured after a second passivation material is deposited and patterned.
When plasma damages are generated as shown in FIGS. 1a and 1b, changes in the device characteristics, such as shifting of a threshold voltage of a transistor, causes changes in the design characteristics. However, the plasma damages are shown in each lot and in each wafer with different tendencies. As a result, it is difficult to control characteristics of the device.
FIGS. 3a and 3b are circuit diagrams illustrating a CMOS inverter in a conventional semiconductor device. Referring to FIGS. 3a and 3b, the CMOS inverter of the conventional semiconductor device includes a plurality of inverters IV1 and IV2.
The inverter IV1 includes a PMOS transistor P1 and a NMOS transistor N1 which are connected serially between a power voltage VDD terminal and a ground voltage VSS terminal. The PMOS transistor P1 and the NMOS transistor N1 receive an input signal IN1 through a common gate and output an output signal OUT1 through a common drain.
The inverter IV2 includes a PMOS transistor P2 and a NMOS transistor N2 which are connected serially between the power voltage VDD terminal and the ground voltage VSS terminal. The PMOS transistor P2 and the NMOS transistor N2 receive an input signal IN2 through a common and output an output signal OUT2 through a common drain.
The inverters IV1 and IV2 are interconnected through a first wring layer 10 in FIG. 3a. As shown in FIG. 3b, the inverters IV1 and IV2 are interconnected through first wiring layers 10a, 10b and through a second wiring layer 20 connected between the first wiring layers 10a and 10b. 
FIG. 4 is a layout diagram illustrating the CMOS inverter of FIG. 3. Referring to FIG. 4, the PMOS transistor P2 of the inverter IV2 is formed in an N-well 30 and the NMOS transistor N2 is formed in a P-well 40. A gate of each transistor is connected to the first wiring layer 10b through a contact node CN1.
When the inverters IV1 and IV2 are interconnected through the first wiring layer 10 as shown in FIG. 3a, a gate layer of the inverter IV2 is connected to a junction for preventing plasma damages during the process after the first wiring layer 10 is formed. However, when the second wiring layer 20 is formed as shown in FIG. 3b, the second inverter IV2 is affected by plasma damages generated from a process for depositing the first wiring layers 10a, 10b and an interlayer insulating film.